1 of 6 19 - 6412; rev 8/12 features ? all - silicon timing cir cuit ? three independent buffered de lays ? stable and precise over tem perature and voltage ? leading and trailing edge precision pr eserves the input symm etry ? vapor p hase and ir reflow sol derable ? ava ilable in tape and reel ? delays specified over both co mmercial and industrial temperature ra nges ? 3v operation ? recommended re placement for ds1033 pin assignment pin description in1 - in3 - input signals out1 - out3 - output signals v cc - +3v supply gnd - ground description the ds1135l series is a low - power, 3v high - speed version of the popular ds1013, ds1033, and ds1035 series. the ds1135l series of delay lines have three independent logic buffered delays in a s ingle pac kage. the device is our fastest 3 - in - 1 delay line. it is available in a 150 - mil 8 -pin so. the device features precise leading and trailing edge accuracy. it has the inherent reli ability of an all - silicon delay line solution. standard delay values are indicated in table 1. ds1135l 3v 3 - in - 1 high - speed silicon delay line ds1135lz 8 -pin so (150 mils) 1 2 3 4 7 8 6 5 in2 gnd in3 in1 v cc out1 out2 out3 downloaded from: http:///
ds1135l 2 of 7 logic diagram figure 1 part number delay table (t plh , t phl ) table 1 part number delay per output (ns) initial tolerance (note 1) tolerance over temp and voltage (note 2) 0c to +70c -40c to +85c ds1135lz-10+ 10/10/10 1.0ns 2 .0ns 3.0 ns ds1135lz-12+ 12/12/12 1.0ns 2 .0ns 3.0 ns ds1135lz-15+ 15/15/15 1.0ns 2 .5ns 4.0 ns ds1135lz-20+ 20/20/20 1.0ns 2 .5ns 4.0 ns ds1135lz-25+ 25/25/25 1.5ns 3.0 ns 5.0 ns ds1135lz-30+ 30/30/30 1.5ns 3.0ns 5.0 ns + denotes a lea d(pb) - free/rohs -compliant package. notes: 1. nominal conditions are +25c and v cc = +3.3v. 2. voltage range of 2.7v to 3.6v. 3. delay accuracies are for both leading and trailing edges. test setup description figure 2 illustrates the hardware configuration used for measuring the timing parameters of the ds1135l. the input waveform is produced by a precision pulse generator under software control. time de lays are measured by a time interval counter (20 ps resolution) connected to the output. the ds1135l output taps are selected and connected to the interval counter by a vhf switch control unit. al l measurements are fully automated with each instrument controlled by the computer over an ieee 488 bus. time delay out in one of three downloaded from: http:///
ds1135l 3 of 7 ds1135l test circuit figure 2 pulse generator unit under test taps 1 -3 start 50 ? stop 50 ? out 3 in vhf switch control unit time interval counter downloaded from: http:///
ds1135l 4 of 7 absolute maximum ratings voltage range on any pin relative to ground -1.0v to +6.0 v short-circuit output current 50ma for 1 second operating temperature range -40c to +85c storage temperature range -55 c to +125 c lead temperature (soldering, 10 seconds) +300c soldering temperature (reflow) +260c this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of t hi s specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (v cc = 2.7 v to 3.6v , t a = - 40 c to +85 c , unless otherwise noted .) parameter symbol conditi on s min typ max units supply voltage v cc 2.7 3.3 3.6 v active current i cc v cc = 3.6v, p eriod = 1 s 10 ma high level input voltage v ih 2.0 v cc + 0.5 v low level input voltage v il -0.5 0.8 v input leakage i l 0v v i v cc -1.0 +1.0 a high level output current i cc v cc = 2.7v, v oh = 2v -1.0 ma low level output current i cc v cc = 2.7v , v ol = 0.4v 8 ma ac electrical characteristics (v cc = 2.7v to 3.6v, t a = - 40 c to +85 c , unless otherwise noted .) parameter symbol min typ max units notes period t period 2 (t wi ) ns input pulse width t wi 100% of delay value ns input- to - ou tput delay t plh , t phl see table 1 ns output rise or fall time t of , t or 2.0 2.5 ns power -up time t pu 1 ms 2 capacitance (t a = + 25 c , unless otherwise noted. ) parameter symbol min typ max units notes input capacitance c in 10 pf downloaded from: http:///
ds1135l 5 of 7 test cond itions ambient temperature: 25 c 3 c supply voltage (v cc ): 3.3v 0.1v input pulse: high: 3.0v 0.1v low: 0.0v 0.1v source impedance: 50 ? max. rise and fall time: 3.0ns max. measured between 0.6v and 2.4v. pulse width: 500ns pulse period: 1 s outpu t load capacitance: 15pf output: each output is loaded with the equivalent of one 74f04 input gate. data is measured at the 1.5v level on the rising and falling edges. note: the above conditions are for test only and do not restrict the devices und er other data sheet conditions. notes: 1. all voltages are referenced to ground. 2. power -up time is the time from the application of power to the time stable delays are being produced at the output. timing diagram t fall 80% t rise 20% in out 1.5v 1.5v t wi t wi period 1.5v 1.5v 1.5v t plh t phl t of t or downloaded from: http:///
ds1135l 6 of 7 terminology period : the time elapsed between the leading edge of the first pulse and the leading edge of th e following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge on the input pulse. t plh (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of the output pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the falling edge of t he input pulse and the 1.5v point on the falling edge of the output pulse. ordering information package informati on for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a + , # , or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertain s to the package regardless of rohs status. package type package code outline no. land pattern no. 8 so s8+2 21 - 0041 90 - 0096 ds1135l package type: z = so (150mil) dash delay (ns) number time 10 10 12 12 15 15 20 20 25 25 30 30 downloaded from: http:///
ds1135l 7 of 7 maxim cannot assume responsibility for use of any circuitry ot her than circuitry entirely embodied in a maxim product. no cir cuit p atent licenses are implied. maxim reserves the right to change the circuitry and specifica tions without notice at any time.the parametric values ( min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1 - 408 - 601 - 1000 ? 2012 maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history revision date description pages changed 8/12 removed the sop package; updated the absolute maximum ratings section ; added the package information section 1, 2, 4, 6 downloaded from: http:///
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